The ever-increasing need for lower cost, higher power density, higher output current, and lower voltage levels for digital electronics such as CPUs, memory, and microcontrollers has boosted demand for higher efficiency converters. This demand has commonly been addressed by DC/DC converters that employ synchronous rectification. To maximize efficiency, these converters use synchronous rectifiers, such as MOSFETs and other low power dissipating devices, instead of output diodes.
When synchronous rectifier MOSFETs are turned on and their controlling driving signal (gate) is not precisely controlled, they will allow current to flow back into the output section of the converter. The MOSFETs will therefore load down any preexisting voltage source connected at their output and parallel operation with current sharing may not be possible. Synchronous rectifiers can even suffer catastrophic failure if they are allowed to conduct an excessive current.
Several different schemes have been proposed for controlling synchronous rectifiers to deal with the problems associated with the negative current in synchronous rectifiers. One approach has been to avoid negative output current through the synchronous rectifier at turn-on by allowing parasitic diodes in the synchronous rectifier MOSFET to perform the rectification and then, depending on the status of a monitoring parameter or a time delay, enabling the synchronous rectifiers. But if the synchronous rectifiers are turned on after a time delay, even with no load, the input current to the converter can be 10 to 20 times higher than those converters with rectifying diodes due to the switching losses of the synchronous rectifier and the negative output current.
Prior art solutions generally rely on some kind of monitoring circuit to sense a chosen parameter, such as current, voltage, temperature, or transformer duty cycle (Zhang, U.S. Pat. No. 6,490,183), and thereby control the synchronous rectifiers and avoid negative current while boosting efficiency. Boylan (U.S. Pat. No. 6,618,274 B2) offers a control scheme for synchronous rectifiers that not only requires the input of the monitor circuit, but also switches from partially synchronous mode to full synchronous mode. These approaches generally result in increased converter cost and complexity, and do not necessarily provide for optimum performance.